1. Field of the Invention
The present invention relates generally to semiconductor technology. More particularly, the present invention relates to a method for fabricating a semiconductor device such as a metal-oxide-semiconductor (MOS) transistor.
2. Description of the Prior Art
Advances in the semiconductor process technologies have dramatically decreased the device feature size and increased the circuit density and performance on integrated circuit chips.
As known in the art, a gate stack or multilayer structure is used as gate electrodes or interconnects in MOS and CMOS integrated circuits. One gate stack that has been proposed consists of doped polysilicon layer and oxide cap layer. The oxide cap layer is patterned and used as a hard mask to subsequently etch the underlying polysilicon layer. After the gate stack is patterned in this manner, the oxide cap layer is temporarily retained in the gate structure. In a later stage, the oxide cap layer is removed to expose the underlying doped polysilicon layer.
A so-called photoresist (PR) approach is typically used in the oxide cap layer removal process for preventing STI (shallow trench isolation) loss. According to this approach, prior to the removal of the oxide mask layer, a layer of photoresist is coated over the substrate surface including the oxide define area and trench isolation region. The photoresist layer is then etched back to reveal the oxide cap layer. One problem associated with this PR approach is that the photoresist layer has serious thickness loading effect between a small pattern such as an isolated gate pattern and a large pattern such as a pad pattern. That is, a thickness of the photoresist layer directly above the large pattern is much greater than that above the small pattern.
Therefore, a need exists for an improved method for forming a semiconductor device such as a metal-oxide-semiconductor (MOS) transistor having a gate structure using oxide cap layer as hard mask, which allows for improved manufacturability and yield.